1. Technical Field of the Invention
The present invention relates generally to a communication receiver and, more particularly, to an apparatus, system and method for digital timing recovery for a receiver in a communication system.
2. Description of Related Art
Matching of modulation and demodulation frequencies in a telecommunication system is made difficult by the physical separation of communication devices where each device is driven by its own local clock. For example, current Asymetrical Digital Subscriber Line (ADSL) systems operate according to Discrete Multitone (DMT) frequency multiplexing where generally only one of the communication devices has a master clock. Typically, the central office modem generates this masterclock. All corresponding client modems are thus required to recover the master clock signal from a communicated data stream for processing, such as sampling, demodulation, and transmission of upstream data to the central office modem.
Generally, the goal of a timing recovery scheme is to synchronize the receiver with the master or remote clock from base clock phase information contained directly or indirectly within the received communication data stream. The receiver translates this phase information to a timing correction. The nature of the correction depends on the type of recovery mechanism. For instance, on a voltage controlled oscillator (VXCO) based system the timing correction corresponds to a updated voltage applied to the VXCO as further described below.
FIG. 1 illustrates a block diagram of a conventional DMT receiver modem 102 in an ADSL system. The modem 102 receives signals from the telephone network at the analog-to-digital converter (ADC) 104 after analog processing. The signals received not only include the communicated data message but also include clock phase information or a pilot tone generated by the transmitting modem to communicate the frequency at which it carried out the modulation of the data message. The received signal is subsequently processed 106 for message recovery for application to a host and for other operations such as timing recovery. For example, the processor 106 extract frequency offset information from the received and convert it into an analog signal through a digital-to-analog converter (DAC) 108. The converted signal is then applied to a voltage controlled oscillator (VCXO) 110 which responds to the analog signal corresponding to the desired frequency to control the ADC 104, such that the time-domain sampling and conversion of the incoming received communication is performed at a frequency that matches that of the transmitting modem.
However, the VCXO 110 implementation is an expensive approach especially on client-side modem systems. Furthermore, fluctuations in the control voltage applied to VCXO 110 by the DAC 108 causes undesirable frequency jitter at the output of the VCXO 110. Reducing this undesirable jitter requires complex circuitry susceptible to age and temperature variation; and creates a phase-locked loop with a narrow frequency operating range. As a result, the conventional modem construction, as shown in FIG. 1, includes expensive oscillator circuitry and requires expensive voltage regulation devices to achieve the timing accuracy needed.